1. Field of the Invention
The present invention relates to an electronic device substrate and its fabrication method, and an electronic device using the electronic device substrate and its fabrication method. Particularly, it relates to an electronic device substrate capable of forming a core-substrateless package with internal electrical wiring, and its fabrication method, and an electronic device using the electronic device substrate and its fabrication method.
2. Description of the Related Art
With technological development in recent years, there is an increasing demand for thin electronic device packages, and electronic devices called core-substrateless package are therefore practically used.
As an example of a general core-substrateless package, JP-A-2004-253674 discloses an electronic device employing a technique using a substrate with a metal electrode connected on a core substrate to mount an electronic component on the substrate, and electrically connect it to a specified electrode with a metal wire, followed by resin sealing and subsequent physical releasing of the core substrate, to expose the metal electrode to the lower surface of the package.
Because this electronic device is covered with sealing resin and has leadless structure that exposes the metal electrode on its backside, a portion corresponding to the substrate comprises the metal electrode only so that the electronic device is very thin.
Also, as an example of another core-substrateless package, JP-A-2004-111536 discloses an electronic device, in which a first wiring layer is arranged on a first interlayer insulating layer, to arrange thereon a second interlayer insulating layer, form a hole in a specified position of this interlayer insulating layer to arrange a via conductor, and sequentially desired times arrange thereon a wiring layer and an interlayer insulating layer with a via conductor, to construct a metallic base frame in laminate.
JP-A-2004-111536 further discloses constructing the electronic device with a general flip-chip fabrication method that subsequently connects a semiconductor to the above substrate via a metallic bump.
According to the structure of JP-A-2004-253674, however, because of no retaining material around the metal electrode, there is the problem that multi-layer wiring is difficult.
Also, according to the structure of JP-A-2004-111536, because of the presence of the interlayer insulating layer, multi-layer wiring is possible, but a very thin substrate such as that disclosed in JP-A-2004-253674 is impossible to fabricate.
Thus there is the first problem of incompatibility between having a very thin substrate such as that of the general core-substrateless package and employing multi-layer wiring structure. This is caused by making the via conductor in making multi-layer wiring structure. The reason for that is as follows.
As mentioned above, although in the structure of JP-A-2004-111536 the multi-layer structure is possible to fabricate because of the presence of the interlayer insulating layer, this multi-layer structure, in which copper is stacked on upper and lower surfaces of the interlayer insulating layer of each single layer plate to form thereon wiring patterns, requires the via conductor to connect the wiring patterns formed on the upper and lower surfaces. This means that the thickness of each single layer plate has to be equal to the thickness of the interlayer insulating layer plus the respective thicknesses of the upper and lower wiring patterns. Further, when a conductive material (typically copper) is formed on the via side surface by plating in the via conductor fabrication process, because of the micro hole, the circulation of the plating liquid is poor, and in addition, it is difficult to grow the plating due to plating application to the insulation, in which case, to ensure connection reliability, its plating thickness is required to be on the order of 10 μm on the wiring patterns, therefore making the wiring patterns combined with the copper wiring patterns originally present typically approximately 25-30 μm thick. When fabricating the multi-layer substrate, the thickness of this wiring pattern is required by the number of wiring layers.
As one method for reducing the size and thickness of electronic device, there is a flip-chip technique that connects an electronic component and a substrate via a bump. This allows size reduction, compared to the case of metallic wire connection of the electronic component and the substrate, because a connection electrode of the substrate can be formed inside the electronic component. Further, forming the above connection with a metallic wire requires height for extending the metallic wire, but the flip-chip technique reduces electronic device thickness because this height may be height of the bump. Because in the flip-chip technique, the electrodes on the electronic component are small in size and dense in spacing by its microfabrication, the electronic device practically has internal wiring formed to the substrate, and an external electrode has to be positioned so that the electronic device can be mounted on a mother board on which the electronic device is to be mounted. For this reason, fabricating in multiple layers the substrate that is as thin and small as that of the general core-substrateless package means that the flip-chip technique may be employed in the general core-substrateless package, and is therefore crucial in promoting size and thickness reduction of the electronic device. Generally, in employing this flip-chip technique, if a bi-wiring-layer comprising one internal wiring layer and one external wiring layer can be realized, it is possible to employ the flip-chip technique.
The second problem is that of manufacturing cost and of global environment protection. It is obvious that the core substrate should be removed in manufacturing the core-substrateless package. In view of JP-A-2004-253674 and JP-A-2004-111536, even though there is the difference between their removal methods, they has to remove the core substrate. The removed core substrate cannot be recycled in both cases of etching removal and physical peeling removal. This is because the core substrate removal has to be performed after the electronic component is mounted and resin-sealed to the substrate with the core substrate. In the manufacturing process of the electronic device, oxidation or strain is caused in the core substrate by heat applied to this device, which results in difficulty recycling. This not only increases manufacturing cost of this core-substrateless package, but also increases waste, therefore also causing problems from the point of view of global environment protection.